1. Field of the Invention
The present invention relates to a method for forming a LOCOS layer in a semiconductor device, and more particularly, to a method for forming a LOCOS layer in a semiconductor device, by which the LOCOS layer is etched in a high voltage region to reduce on-state resistance.
2. Discussion of the Related Art
A system with a single semiconductor chip has improved with an increase in the integration of semiconductor diodes and other devices and with design techniques that have developed as a result. The single chip system may integrate a controller, a memory, and other circuitry, which operate at relatively low voltages. To achieve greater miniaturization, however, the chip may also integrate circuitry for power source control, i.e., a single circuit having input and output terminals, but since high voltages may be applied to the input and output terminals, the chip should employ internally a high-voltage power transistor as the input/output device, rather than traditional CMOS circuitry, which operates at much lower voltages. That is, the circuitry associated with the input and output terminals of the power source and the controller should also be incorporated into the single chip to reduce system size and weight.
Accordingly, to integrate into a single chip both a high-voltage transistor and a low-voltage CMOS transistor circuit, a lateral double-diffused MOS transistor is obtained by enhancing the structure of a vertical double-diffused MOS transistor, which is a conventional discrete power transistor. The drain of a lateral double-diffused MOS transistor is arranged horizontally to generate a horizontal current flow, and a drift region disposed between the drain and channel is provided to secure a higher breakdown voltage.
FIG. 1 illustrates a contemporary local oxidation of silicon layer, which is commonly known as a LOCOS layer. Here, a gate poly 20 is stacked on the LOCOS layer 10 in a high voltage region and prevents a concentration of an electrical field at the surface of the high voltage region, thereby preventing surface breakdown. In this case, however, the length of a current transfer path from a source 30 to a drain 40 is increased, thereby increasing correspondingly the on-state resistance and possibly deteriorating current driving capability.